Let’s begin from the definition: setup time is the minimum time before active edge of the clock that the input data of flip-flop needs to become stable to its new value.
Why do the flip-flops need a setup time in the first place, and what’s actually going on during this time? Flip-flops (and other logic based memory elements) usually have a loop to lock the value in, this provides retention even when the input has changed. In short, its the settling time delays for nodes in the loops that dictate setup time.
I’ll try to illustrate setup time requirement with a concrete example, using a Master-Slave D flip-flop. The circuit schematic is shown in Figure 1.
While CLK=0 i.e. a positive edge is about to occur, the flip-flop transmission gates are in the state shown in Figure 2.
Before the clock goes to 1, the D input needs to propagate through the two inverters and nodes a, b. This path is what determines the setup time of a flip-flop, and is shown highlighted in Figure 3.
Now, let us consider an example of a setup time failure. Imagine enough setup time was not allowed and the node b is still at old value when the positive clock edge arrives. This situation is shown in Figure 4, notice that second inverter on the path has not yet driven node b to its new value.
When the positive clock edge arrives, the Master Latch can go metastable as the node b attempts to drive old value and has contention against node a. This metastability will propagate out on the Q of flip-flop. Figure 5 shows the possible situation after positive clock edge.
A quick follow-up question: do you think setup time failure is dangerous if the D of flip-flop was equal to Q?
During an interview, I also like to test using various other flavors and implementations of a flip-flop.