Tag: sythesis

break statement in synthesizable Verilog

Generally speaking, break/continue statements find use in simulation purposes – notably in building test-benches. However, modern synthesis tools allow you to make use of these in your design as well! Following is a really cool example of how to make use of break to describe a Priority Multiplexer. Let’s begin from the truth table:

s0 s1 s2 .. sn out
1 x x x x x0
0 1 x x x x1
0 0 1 x x x2
0 0 0 0 x xn
Truth table for a Priority Multiplexer

The corresponding schematic looks as follows:

Priority Multiplexer schematic

Now comes the cool part – following RTL snippet cleverly using break statement can be used to realize the above schematic.

always_comb begin
  out = x[N];
  for (int i = 0; i < N; i++ ) begin
          if (s[i]) begin
               out = x[i];
               break ;
          end
  end
end